`include "defines.v"
module ysyx_210448_IF_ID (
  input wire clk,
  input wire rst,
  input wire if_id_en,
  input wire if_id_bubble,
  input wire if_mem_read,
  input wire [63 : 0] if_pc,
  input wire [31 : 0] if_inst,
  input wire if_w_ena,
  input wire if_fetched,
  output reg [63 : 0] id_pc,
  output reg id_mem_read,
  output reg [31 : 0] id_inst,
  output reg id_w_ena,
  output reg id_fetched
 
);
//bubble 气泡，清空寄存器
    always @(posedge clk) begin

        if(rst==1'b1)
        begin
            id_pc<=64'b0;
            id_inst<=32'b0;
            id_fetched<=1'b0;
            id_mem_read<=1'b0;
            id_w_ena<=1'b0;
        end
        else if(if_id_en)
        begin
            if(if_id_bubble==1'b1)
            begin
            id_pc<=64'b0;
            id_inst<=32'b0;
            id_fetched<=1'b0;
            id_mem_read<=1'b0;
            id_w_ena<=1'b0;
            end
            else
            begin
            id_inst<=if_inst;
            id_pc<=if_pc;
            id_fetched<=if_fetched;  
            id_mem_read<=if_mem_read;
            id_w_ena<=if_w_ena;
            end
        end
    end
    

endmodule

